Fabless: The Transformation of the Semiconductor Industry

As most of you know, Paul McLellan, Beth Martin, and I published a book last year which is a really nice history of the fabless semiconductor ecosystem

Preface

The purpose of this book is to illustrate the magnificence of the fabless semiconductor ecosystem, and to give credit where credit is due. Business models, as much as the technology, are what keep us thrilled with new gadgets year after year, and focused on the evolution of the electronics business. These “In Their Own Words” chapters allow the heavyweights of the industry to tell their corporate history for themselves, focusing on the industry developments (both in technology and business models) that made them successful, and how they in turn drive the further evolution of the semiconductor industry.

The economics of designing a chip and getting it manufactured is similar to how the pharmaceutical industry gets a new drug to market. Getting to the stage that a drug can be shipped to your local pharmacy is enormously expensive. But once it’s done, you have something that can be manufactured for a few cents and sold for, perhaps, ten dollars. ICs are like that, although for different reasons. Getting an IC designed and manufactured is incredibly expensive, but then you have something that can be manufactured for a few dollars, and put into products that can be sold for hundreds of dollars. One way to look at it is that the first IC costs many millions of dollars—you only make a lot of money
if you sell a lot of them.

What we hope you learn from this book is that even though IC-based electronics are cheap and ubiquitous, they are not cheap or easy to make. It takes teams of hundreds of design engineers to design an IC, and a complex ecosystem of software, components, and services to make it happen. The fabs that physically manufacture the ICs cost more to build than a nuclear power plant. Yet year after year, for 40 years, the cost per transistor has decreased in a steady and predictable curve. There are many reasons for this cost reduction, and we argue that the fabless semiconductor business model is among the most important of those reasons over the past three decades. The next chapter is an introduction to the history of the semiconductor industry, including the invention of the basic building block of all modern digital devices, the transistor, the invention of the integrated circuit, and the businesses that developed around them.

Table of Contents
Chapter 1: The Semiconductor Century
Chapter 2: The ASIC Business
In Their Own Words: VLSI Technology
In Their Own Words: eSilicon Corporation
Chapter 3: The FPGA
In Their Own Words: Xilinx
Chapter 4: Moving To The Fabless Model
In Their Own Words: Chips And Technologies
Chapter 5: The Rise Of The Foundry
In Their Own Words: TSMC And Open Innovation Platform
In Their Own Words: GLOBALFOUNDRIES
Chapter 6: Electronic Design Automation
In Their Own Words: Mentor Graphics
In Their Own Words: Cadence Design Systems
In Their Own Words: Synopsys
Chapter 7: Intellectual Property
In Their Own Words: ARM
In Their Own Words: Imagination
Chapter 8: What’s Next For The Semiconductor Industry

FABLESS: THE TRANSFORMATION OF THE SEMICONDUCTOR INDUSTRY - Click here

Synopsys to Acquire Atrenta

There have been lots of rumors about potential suitors for Atrenta, not just recently but over the years. Since they operate at the RTL and IP level there is clearly potential for other companies than the usual suspects of Cadence, Synopsys and Mentor. Two that have been much-rumored were ANSYS (who acquired Apache a few years ago) and Dassault (who have some process management solutions and acquired Tuscany Design Automation [disclosure: I was on the board] right at the end of 2012). I've never heard it mentioned but another possible candidate might have been TSMC who have used Atrenta's SpyGlass solution as their "signoff" tool for IP qualification as part of their OIP ecosystem.

The financial details of the deal were not disclosed. But for sure it was not a fire sale. For a start, the current threshold for HSR filing, the so-called "$50M threshold", is actually $76.3M this year so we know that the price was at least that high.

However, since there were multiple companies rumored to be interested I think it is logical to speculate that the price will be at a reasonable multiple on their revenue, itself rumored to be running in the $60M range. At 3.5X revenue that would be $210M so I'll go with that as my guess. Final answer.

Of course Synopsys plans to integrate the Atrenta technology into their verification continuum, especially SpyGlass which has wide acceptance. Manoj Ghandi, who is the GM of verification, adds a bit of color (not much, to be honest):

Atrenta's demonstrated leadership in static and formal technologies is recognized throughout the EDA industry, and its technology is used by design and verification teams around the world. Synopsys expects to leverage this strong technology to further improve our Verification Continuum platform to address continually increasing verification challenges, and to support our ongoing R&D collaborations with customers in both verification and implementation.

Atrenta will be at DAC on booth #1732. Interestingly they just announced the date of their user conference in October. Of course that may take place, since under the rules for an acquisition like this the two companies are not really able to work together until the deal is closed (on the basis that if the deal is struck down then everything should go back to exactly how it was before). However, I think it is more likely that it will just get folded into SNUG.

The Synopsys press release is here.

3 Reasons behind Intel to buy Altera FPGA

While Altera FPGA aren't as fast as Intel's own Xeon processors, they are more flexible and are used in a number of industries including consumer electronics, telecommunications, and automotive. By securing Altera, Intel can step into IoT applications.Industry analysts believe that Avago's purchase of Broadcom may have propelled Intel to make a second attempt at Altera.

These are some key factors which may have influenced Intel's decision to purchase Altera.

1) Altera FPGA will be used in Intel's processor chips. The purchase allows Intel to enter the SoC market.

Some analysts feel that the price tag of $17 billion was overvalued, but Intel defended its to buy Altera FPGA stating that they allow for faster speeds in Intel's processor chips.

2) Intel's purchase of Altera has a negative impact on its competitors, including IBM and ARM. IBM and ARM will need to rely on another FPGA source - such as Xilinx FPGA, Microsemi or Lattice Semiconductor.

3) Intel has the opportunity to reach out to other markets.

Avago's purchase of Broadcom has propelled Qualcomm to consider other new opportunities. Qualcomm's reach into the mobile chip market is severely limited by the consolidation between the two companies. Both Avago and Intel have mutual interests in the mobile chip market, and industry analysts believe that a partnership between Qualcomm and Intel is a viable step.

UltraScale FPGA scales to 600 million gates

Pro Design has come up with a kit for prototyping Xilinx Virtex UltraScale XCVU440 FPGAs and will demonstrate it at next month’s Design Automation Conference (DAC) in San Francisco.

Scalable from 1 up to 4 pluggable Xilinx Virtex UltraScale XCVU440 based FPGA modules the Quad system offers a capacity of up to 120 million Asic gates. Up to five Quad systems with overall 20 FPGA modules can be easily connected together to increase the capacity up to 600 million gates.

Pro Design also has a development system called Uno for IP or sub designs development and can reuse the FPGA modules for complete SoC and Asic prototyping by plugging the same proFPGA Virtex 7 or UltraScale FPGA modules on a Duo or Quad motherboard.

There are also motherboards, FPGA modules, daughter cards and accessories which can be used in combination with the proFPGA XCVU440 FPGA modules.The system comes with the proFPGA Builder software, which provides an extensive set of features, like advanced clock management, integrated self- and performance test, automatic board detection and I/O voltage programming, system scan- and safety mechanism, and quick remote system configuration and monitoring through USB, Ethernet or PCIe, which simplifies the usage of the proFPGA system tremendously.

The systems are available for early adopter customers with general availability in Q4 2015.

Accelerating PCB Design and Manufacturing

In modern electronic industry PCBs are required to accommodate highly dense circuits with large number of components and complex routing spaces. While the complexity is increasing, the time-to-market is decreasing. In such a scenario, there is no other option than to reduce the design time by employing innovative editing options and make the design correct-by-construction for manufacturing so that the cycles between design and manufacturing are eliminated. Moreover, designs may need customized rules which should be easy to develop and use. Also, frequent changes in fabrication technologies require new rules to be developed in a timely manner. It’s very pleasant to see that with rapid increase in circuit sizes and complexities, PCB tools and technologies have also evolved by a large extent.

A few days ago Cadence released its Allegro 16.6-2015 product portfolio that introduced several new capabilities to address modern day challenges in PCB designs, make designs more predictable, and shorten the overall design time up to manufacturing.

Allegro provides an integrated environment for electrical, physical and manufacturing verification. In Allegro 16.6, the Allegro Manufacturing Option includes DFM (Design for Manufacturing) Checker, Documentation Editor, and Panel Editor. The DFM Checker provides manufacturing analysis tools for designers to analyze and correct fabrication related issues before sending the design for fabrication, thus eliminating cycles between design and fabrication and making the design more predictable. The Documentation Editor is an intelligent documentation-authoring tool that automates the complete process for fabrication documentation. It creates the complex PCB documentation for handoff to manufacturing in a fraction of time compared to traditional way of documentation. This is streamlines manufacturing handoff eliminating unnecessary scrap and iterations with manufacturing partners. The Panel Editor automates the complex process of assembly panel documentation. It enables designers to quickly create manufacturing documents that clearly articulate the panel specification and instructions for successful fabrication, assembly, and inspection of their designs. Cadence customers have observed this efficient fabrication and assembly document generation process to be faster than traditional methods by 60% or more.

The Allegro Rules Developer and Checker provides flexibility to extend supported rule sets. It provides a ‘relational geometric verification language’ designed specifically for creating rules that are proprietary and custom to an original equipment manufacturer (OEM). The tool supports constraint driven flow where the rules can be viewed and executed from the Allegro Constraint Manager making it a single source for all DRCs within a PCB. This also enables designers develop new rules according to changing fabrication processes or even new fabrication technologies.

The Allegro 16.6 provides excellent capabilities for routing and tuning high-speed interfaces such as DDR3, DDR4, PCIe, and so on. These interfaces operate at high bandwidth and low voltage, and are increasingly susceptible to crosstalk. The timing closure is a significant challenge for such a high-speed interface. The routing for such high-speed interface is accomplished under complex set of electrical and layout implementation constraints.

Allegro PCB Editor has added several new capabilities to improve designers’ productivity and accelerate timing closure. These include ‘adding ground current return path vias to differential pairs during Add Connect’, ‘creating off-angle routes to avoid FR4 fiber weave coupling and achieve better impedance control’, ‘improved arc support in routing’, and many others.

There is auto-connect routing where a designer can select a set of signals and the route engine creates flow automatically. The ‘Adjust Spacing’ capability allows users to compress spreading of traces in the trunk of a set of signals.

There is a powerful shape editing environment to quickly create and modify shapes and save lot of time in designing power delivery networks and other complex layout editing. Designers can add notches, join edges, slide edges with corners, move multiple segments with one command, convert corners, and so on.

Overall Allegro 16.6-2015 portfolio provides a powerful and ideal PCB design platform for modern day PCB designs that need fast turnaround to meet ever shrinking time-to-market window. To know more read the press release here.

Intel plans to buy Altera FPGA for a $16 billion deal

Currently, Intel supplies Atom and Xeon processors for computing solutions.By acquiring Altera, Intel aims to target data-intensive networking centers at major companies such as Google, Facebook, LinkedIn and Ebay. FPGA solutions are desirable because they increase performance and consume less power. For data centers that are built to maximize efficiency, a high performance, low-cost solution is ideal.Intel's second aim is to target the faster growing mobile market. This market includes smartphones, tablets, and wearable technology. The demand and turnover for products in this market is much higher compared to computing devices. Mobile device makers rely on FPGA to power their products. FPGA used in mobile technology devices are available at low per unit costs.